复习考博中间看的，还记得躺在床上翻书的日子。

highlights #

• 2015-08-01 22:52:35
• There are certain instructions in the instruction stream, however, that allow the processor to jump to a program line that is out of sequence.
• 2015-08-01 23:42:01
• peripherals
• 2015-08-02 12:26:23
• crunching
• 2015-08-02 12:29:41
• sport utility vehicle (SUV).
• Note SUV
• 2015-08-02 12:30:05
• chassis
• 2015-08-02 12:35:13
• fiscal
• 2015-08-02 12:36:38
• brute
• 2015-08-02 12:37:51
• billable
• 2015-08-02 12:40:07
• fivefold
• 2015-08-02 12:40:02
• nutshell
• 2015-08-02 15:15:29
• Pipelining works its magic by making optimal use of already existing resources.
• 2015-08-02 15:32:38
• stems
• 2015-08-02 15:40:32
• Thus pipelining doesn’t speed up instruction execution time, but it does speed up program execution time (the number of nanoseconds that it takes to execute an entire program)
• 2015-08-02 15:46:53
• Because pipelining requires that each pipeline stage take exactly one clock cycle to complete, the clock cycle can now be shortened to 0.5 ns in order to fit the lengths of the eight pipeline stages.
• 2015-08-03 07:40:12
• plummet
• 2015-08-03 07:46:28
• An instruction’s latency is the number of clock cycles it takes for the instruction to pass through the pipeline.
• 2015-08-03 07:47:53
• In real-world processors, instruction latency is not necessarily a fixed number that’s equal to the number of pipeline stages.
• 2015-08-03 07:51:26
• minimum instruction latencies.
• 2015-08-03 09:53:07
• Main memory accesses are a major cause of pipeline stalls,
• 2015-08-03 10:06:54
• The RS6000 from IBM was released in 1990 and was the world’s first commercially available superscalar CPU.